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HM62256B Series
256k SRAM (32-kword x 8-bit)
ADE-203-135F (Z) Rev. 6.0 Nov. 13, 1997 Description
The Hitachi HM62256B Series is a CMOS static RAM organized 32,768-word x 8-bit. It realizes higher performance and low power consumption by employing 0.8 m Hi-CMOS process technology. The device, packaged in 8 x 14 mm TSOP, 8 x 13.4 mm TSOP with thickness of 1.2 mm, 450 mil SOP (foot print pitch width), 600 mil plastic DIP, or 300 mil plastic DIP, is available for high density mounting. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems.
Features
* Single 5.0 V supply: 5.0 V 10% * Access time: 55 ns/70 ns/85 ns (max) * Power dissipation: Active: 25 mW (typ) (f = 1 MHz) Standby: 1.0 W (typ) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Common data input and output Three state output * Directly TTL compatible all inputs and outputs * Battery backup operation
HM62256B Series
Ordering Information
Type No. HM62256BLP-7 HM62256BLP-7SL HM62256BLSP-7 HM62256BLSP-7SL HM62256BLFP-7T HM62256BLFP-5SLT HM62256BLFP-7SLT HM62256BLFP-7ULT HM62256BLT-8 HM62256BLT-7SL HM62256BLTM-8 HM62256BLTM-5SL HM62256BLTM-7SL HM62256BLTM-7UL Access time 70 ns 70 ns 70 ns 70 ns 70 ns 55 ns 70 ns 70 ns 85 ns 70 ns 85 ns 55 ns 70 ns 70 ns 8 mm x 13.4 mm 28-pin TSOP (TFP-28DA) 8 mm x 14 mm 32-pin TSOP (TFP-32DA) 450-mil 28-pin plastic SOP (FP-28DA) 300-mil 28-pin plastic DIP (DP-28NA) Package 600-mil 28-pin plastic DIP (DP-28)
Pin Arrangement
HM62256BLP/BLFP/BLSP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
2
HM62256B Series
Pin Arrangement (cont.)
HM62256BLT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) HM62256BLTM Series
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2
22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top view)
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2
Pin Description
Pin Name A0 to A14 I/O0 to I/O7 CS WE OE VCC VSS NC Function Address input Data input/output Chip select Write enable Output enable Power supply Ground No connection
3
HM62256B Series
Block Diagram
VCC VSS
* * * * * * * *
(MSB) A12 A5 A7 A6 A8 A13 A14 A4 (LSB) A3 Memory Matrix 512 x 512
Row Decoder
* *
I/O0
* * * * *
* * * * * * *
Column I/O Column Decoder
* *
Input Data Control
* * *
I/O7
(LSB)
A2 A1 A0 A10 A9 A11
* *
(MSB)
* *
CS WE OE
Timing Pulse Generator Read/Write Control
4
HM62256B Series
Operation Table
WE x H H L L CS H L L L L OE x H L H L Mode Standby Output disable Read Write Write VCC current I SB , I SB1 I CC I CC I CC I CC I/O pin High-Z High-Z Dout Din Din Ref. cycle -- -- Read cycle (1)to (3) Write cycle (1) Write cycle (2)
Note: x: H or L
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5* to V CC+0.3* 1.0 0 to +70 -55 to +125 -10 to +85
1 2
Unit V V W C C C
Notes: 1. VT min: -3.0 V for pulse half-width 50 ns 2. Maximum voltage is 7.0 V
DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Note: VIH VIL Min 4.5 0 2.2 -0.5*
1
Typ 5.0 0 -- --
Max 5.5 0 VCC + 0.3 0.8
Unit V V V V
Notes
1. VIL min: -3.0 V for pulse half-width 50 ns
5
HM62256B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating current Average HM62256B-5 operating current HM62256B-7 HM62256B-8 Symbol Min |ILI| |ILO | I CC I CC1 -- -- -- -- Typ*1 -- -- 6 -- Max 1 1 15 60 Unit A A mA mA Test conditions Vin = VSS to V CC CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC CS = VIL, Others = VIH/VIL, II/O = 0 mA Min cycle, duty = 100%,II/O = 0 mA, CS = VIL, Others = VIH/VIL
I CC1 I CC1 I CC2
-- -- -- -- -- -- -- -- 2.4
33 29 5 0.3 0.2 0.2* 0.2* -- --
2 3
60 50 15 2 100 50* 10* 0.4 --
2 3
mA mA mA mA A A A V V I OL = 2.1 mA I OH = -1.0 mA Cycle time = 1 s, II/O = 0 mA, CS = VIL, VIH = VCC, VIL = 0 CS = VIH Vin 0 V, CS V CC - 0.2 V
Standby current
I SB I SB1 I SB1 I SB1
Output low voltage Output high voltage
VOL VOH
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. This characteristic is guaranteed only for L-SL version. 3. This characteristic is guaranteed only for L-UL version.
Capacitance (Ta = 25C, f = 1.0 MHz)
Parameter Input capacitance*
1 1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 8 10
Unit pF pF
Test Conditions Vin = 0 V VI/O = 0 V
Input/output capacitance* Note:
1. This parameter is sampled and not 100% tested.
6
HM62256B Series
AC Characteristics (Ta = 0 to +70C, VCC = 5.0 V 10%)
Test Conditions * * * * Input pulse levels: 0.8 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (50 pF) (HM62256B-5) 1 TTL Gate + C L (100 pF) (HM62256B-7/8) (Including scope & jig)
Read Cycle
HM62256B -5 Parameter Read cycle time Address access time Chip select to access time Output enable to output valid Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Output hold from address change Symbol t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH Min 55 -- -- -- 5 5 0 0 5 Max -- 55 55 35 -- -- 20 20 -- -7 Min 70 -- -- -- 10 5 0 0 5 Max -- 70 70 40 -- -- 25 25 -- -8 Min 85 -- -- -- 10 5 0 0 5 Max -- 85 85 45 -- -- 30 30 -- Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes
7
HM62256B Series
Write Cycle
HM62256B -5 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output disable to output in High-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 55 40 0 40 35 0 0 25 0 5 0 Max -- -- -- -- -- -- 20 -- -- -- 20 -7 Min 70 60 0 60 50 0 0 30 0 5 0 Max -- -- -- -- -- -- 25 -- -- -- 25 -8 Min 85 75 0 75 55 0 0 35 0 5 0 Max -- -- -- -- -- -- 30 -- -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 8 4, 13 7 1, 2, 8 5 6 Notes
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. Address must be valid prior to or simultaneously with CS going low. 4. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition of CS going low or WE going low. A write ends at the earliest transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from CS going low to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS or WE going high to the end of write cycle. 8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 10. Dout is the same phase of the latest written data in this write cycle. 11. Dout is the read data of next address. 12. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP tDW min + tWHZ max
8
HM62256B Series
Timing Waveform
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address tAA tACS
CS tOH tOE tOLZ OE tOHZ tCHZ Dout High impedance Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL )
tRC Address tAA tOH Dout Valid data Valid address tOH
9
HM62256B Series
Read Timing Waveform (3) (WE = VIH, OE = VIL )*3
tACS CS tCLZ High impedance
tCHZ Valid data
Dout
Write Timing Waveform (1) (OE Clock)
tWC Address Valid address tAW OE tCW CS
*9
tWR
tAS WE tOHZ Dout
tWP
High impedance tDW tDH Valid data
Din
High impedance
10
HM62256B Series
Write Timing Waveform (2) (OE Low Fixed)
tWC Address
Valid address tCW tWR
CS
*9
tAW tWP WE tAS tWHZ Dout tDW Din High impedance tDH
*12
tOH
tOW
*10
*11
Valid data
11
HM62256B Series
Low VCC Data Retention Characteristics (Ta = 0 to 70C)
Parameter VCC for data retention Data retention current Symbol VDR I CCDR I CCDR I CCDR Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. 5. 6. t CDR tR Min 2.0 -- -- -- 0 t RC* 5 Typ* 1 -- 0.05 0.05 0.05 -- -- Max 5.5 30* 2 10* 3 3* -- --
4
Unit V A A A ns ms
Test conditions*6 CS V CC - 0.2 V, Vin 0V VCC = 3.0 V, Vin 0V CS V CC - 0.2 V
See retention Waveform
Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 10 A max. at Ta = 0 to +40C. This characteristic is guaranteed only for L-SL version, 3 A max. at Ta = 0 to +40C. This characteristic is guaranteed only for L-UL version, 0.6 A max. at Ta = 0 to +40C. t RC = Read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.
Low V CC Data Retention Timing Waveform
Data retention mode VCC 4.5V tCDR 2.2V VDR CS 0V CS VCC - 0.2V tR
12
HM62256B Series
Package Dimensions
HM62256BLP Series (DP-28)
Unit: mm
28 35.6 36.5 Max 15
1
1.2 1.9 Max
14 2.54 Min 5.70 Max 15.24
0.51 Min
13.4 14.6 Max
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-28 -- Conforms 4.6 g
13
HM62256B Series
Package Dimensions (cont.)
HM62256BLSP Series (DP-28NA)
Unit: mm
36.00 28 37.32 Max 15
7.40 Max
1
2.20 Max
1.30
14 5.08 Max
7.10
7.62
0.51 Min
2.54 Min
0.25 - 0.05 0 - 15
DP-28NA -- Conforms 2.2 g
+ 0.11
2.54 0.25
0.48 0.10
Hitachi Code JEDEC EIAJ Weight (reference value)
14
HM62256B Series
Package Dimensions (cont.)
HM62256BLFP Series (FP-28DA)
Unit: mm
18.00 18.75 Max 28 15 8.40 1 1.12 Max 14 3.00 Max
0.17 0.05 0.15 0.04
11.80 0.30
1.70
0 - 8 1.00 0.20
1.27 0.15
0.40 0.08 0.38 0.06
0.20 M
Hitachi Code JEDEC EIAJ Weight (reference value) FP-28DA Conforms Conforms 0.82 g
Dimension including the plating thickness Base material dimension
0.15 0.20 + 0.10 -
15
HM62256B Series
Package Dimensions (cont.)
HM62256BLT Series (TFP-32DA)
Unit: mm 8.00 8.20 Max 32 17 12.40 1 16 0.50 0.22 0.08 0.20 0.06 0.08 M 14.00 0.20 0 - 5 0.80 0.45 Max 1.20 Max 0.17 0.05 0.125 0.04
0.13 0.05
0.10
0.50 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-32DA Conforms Conforms 0.26 g
16
HM62256B Series
Package Dimensions (cont.)
HM62256BLTM Series (TFP-28DA)
Unit: mm 8.00 8.20 Max 21 8
22
28 1
7 0.55 0.10 M 0.63 Max 13.40 0.30 0 - 5 0.80
0.22 0.05 0.20 0.04
11.80
1.20 Max
0.145 0.05 0.125 0.04
0.10
0.05 -0.05
+0.10
0.50 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-28DA -- -- 0.22 g
17
HM62256B Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
18
HM62256B Series
Revision Record
Rev. 0.0 1.0 2.0 Date Sep. 10, 1993 Mar. 23, 1994 Oct. 31, 1994 Contents of Modification Initial Issue DC Characteristics I CC1 Typ: --/--/--/-- mA to 33/29/26/24 mA Deletion of HM62256BLT-7/10SL/12SL Addition of HM62256BLTM-8/7SL/8SL(TFP-28DA) AC Characteristics Addition of note 12 Low VCC data retention characteristics VDR max: -- to 5.5 V Note 2: 20 A max at Ta = 0 to +40C to 10 A max at Ta = 0 to +40C Deletion of description; (only for L-version) Drawn by Y. Saito Y. Saito Y. Saito Approved by K. Yoshizaki K. Yoshizaki K. Yoshizaki
3.0
Jun. 19, 1995
M. Higuchi Change of format Deletion of HM62256BLP-8/10/12/8SL/10SL/12SL Deletion of HM62256BLSP-8/10/12/8SL/10SL/12SL Deletion of HM62256BLFP-8T/10T/12T Deletion of HM62256BLFP-8SLT/10SLT/12SLT Deletion of HM62256BLT-10/12/8SL Deletion of HM62256BLTM-8SL Addition of HM62256BLFP-4SLT/5SLT/7ULT Addition of HM62256BLTM-4SLT/5SLT/7ULT Features Fast access time: 70/85/100/120 ns to 45/55/70/85 ns DC Characteristics I CC1 typ: 33/29/26/24 mA to --/--/33/29 mA max: 60/50/50/45 mA to 70/60/60/50 mA I SB1 typ: 0.3/0.3 A to 0.2/0.2/0.2 A max: 100/50 A to 100/50/10 A Addition of note 3 AC Characteristics Change order of notes. Test Condition Addition of HM62256B-4: 1TTL Gate + CL (100pF) (Including scope & jig) t RC min: 70/85/100/120 ns to 45/55/70/85 ns t AA max: 70/85/100/120 ns to 45/55/70/85 ns t ACS max: 70/85/100/120 ns to 45/55/70/85 ns t OE max: 40/45/50/60 ns to 30/35/40/45 ns t CLZ min: 10/10/10/10 ns to 5/5/10/10 ns t OHZ max: 25/30/35/40 ns to 20/20/25/30 ns t OH min: 5/5/10/10 ns 5/5/5/5 ns t WC min: 70/85/100/120 ns to 45/55/70/85 ns t CW min: 60/75/80/85 ns to 35/40/60/75 ns t AW min: 60/75/80/85 ns to 35/40/60/75 ns t WP min: 50/55/60/70 ns to 30/35/50/55 ns t WHZ max: 25/30/35/40 ns to 20/20/25/30 ns
K. Yoshizaki
19
HM62256B Series
Revision Record (cont.)
Rev. 3.0 Date Jun. 19, 1995 Contents of Modification AC Characteristics t PW min: 30/35/40/50 ns to 20/25/30/35 ns t OHZ max: 25/30/35/40 ns to 20/20/25/30 ns Low VCC Data Retention Characteristics Addition of note 4. t CCDR typ: 0.2/0.2 A to 0.05/0.05/0.05 A max: 30/10 A to 30/10/3 A Ordering Information (HM62256BLFP-4 Series) Addition of note (Under development) AC Characteristics Test Conditions HM62256-5/7/8:1TTL Gate + CL (100pF) to HM62256-5:1TTL Gate + CL (50pF) and HM62256-7/8:1TTL Gate + CL (100pF) Change of format Deletion of HM62256B-4 Series Operation Table Correct Error DC Operating Conditions Correct Error DC Characteristics Correct Error Drawn by M. Higuchi Approved by K. Yoshizaki
4.0
Nov. 29, 1995
M. Higuchi
K. Yoshizaki
5.0 6.0
Jul. 9, 1997 Nov. 13,1997
M. Higuchi
K. Imato
20

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